Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits -Part II
Résumé
This paper gives a detailed insight on a machine learning procedure to infer quasistatic quantities of ElectroStatic Discharge (ESD) protection structures from their instance parameters in a netlist. It resorts to a dataset of Transmission Line Pulse (TLP) I-V curves that have been obtained from numerous transient electrical simulations. The tuning of machine learning algorithms and the quantification of their generalized prediction performances on out-of-sample data are performed by means of nested cross-validation. Resulting fitted analytical models are encompassed in a tool called ESD IP Explorer in charge of providing a systematic and scalable ESD verification methodology. This tool, which has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures, is described in a former article Viale2020.