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Conference Papers Year : 2020

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Abstract

To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).
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Dates and versions

hal-02416253 , version 1 (03-01-2020)

Identifiers

  • HAL Id : hal-02416253 , version 1

Cite

Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy. Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models. ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Jan 2020, Beijing, China. pp.1-6. ⟨hal-02416253⟩
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