The first task of Non-Binary decoders (LDPC or Turbo) is to generate the Log-Likelihood Ratio (LLR) of the received Non-Binary symbols defined over Galois Fields GF(q >2). In the Extended Min-Sum decoding algorithm, the intrinsic information associated to a given received symbol is a sorted list of the nm most reliable Non-Binary GF symbols along with their associated reliability values. In this paper we present a fully parallel LLR generation algorithm, an enabler for very high throughput decoding, that processes one received symbol per clock cycle. We provide complexity figures for LLR architectures designed over GF(q) of sizes 64, 256 and 1024, as well as different values of nm. Compared to the related state of the art architecture, FPGA synthesis results show that the proposed parallel architecture improves the hardware efficiency by a factor ranging from 7 up to 15.