Deterministic scheduling reconciles cache with preemption for WCET estimation
Résumé
Inertial Reference Systems are highly critical in the avionics context. As a result, their software components are submitted to a rigorous demonstration of the Worst-Case Execution Time (“WCET”), together with a demonstration of “robust” partitioning. With a processor using cache memory, if task scheduling is preemptive, these demonstrations become a real challenge. The difficulty comes in adequately bounding the cache refill cost due to context switches. This paper presents the solution we have adopted on our new generation of Inertial Reference Systems: it consists in a particular scheduling policy, which allows in turn a particular cache management policy. This cache policy is a key point for performance, because modern processors rely radically on cache to achieve the promised MIPS: the result is – to our knowledge – an unrivalled use of cache on a DAL A system. Lastly, the new scheduling policy puts the final touch to our lock-free inter-task communication protocol.
Origine | Fichiers produits par l'(les) auteur(s) |
---|
Loading...