ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based implementation of a high throughput flexible turbo decoder. It introduces turbo decoding application and proposes an Application-Specific Instruction-set Processor with SIMD architecture, a specialized and extensible instruction-set, and 6-stages pipeline control. The proposed ASIP is developed in LISA language and generated automatically using the Processor Designer framework from CoWare. The paper illustrates how the automatic generated RTL code of the ASIP can be adapted for a rapid prototyping on PPGA reconfigurable logic and memory resources. Tor a Xilinx Virtex-II Pro PPGA, a single ASIP prototype occupies 68% of PPGA resources and achieves a 6.3 Mbit/s throughput when decoding a double binary turbo code with 5 iterations.