The increasing demand of high data rate and reliability in modern communication systems is pushing next-generation standards toward error correction schemes allowing high throughput decoding with near Shannon limit performance. Thus, data rates above 1Gb/s and 10Gb/s will be required for the next generation standards of wireless technologies (WIFI, WIMAX, DVB-H…) and data transmission over Passive Optical Networks (PON), respectively. In order to achieve high throughput and to reduce latency, parallel implementations become mandatory. A full-parallel architecture for the turbo decoding of product codes was previously proposed. The major advantage of this full-parallel architecture is that it enables the memory block between each half-iteration to be replaced by simple interconnection networks. In this context, the use of single-error-correcting Reed-Solomon (RS) product codes was investigated in an ultra high-speed context. In this paper, the implementation onto FPGA devices of an ultra high throughput (31,29)2 RS turbo decoder is presented. The purpose of this prototype is to demonstrate that an RS turbo decoder can effectively achieve data rates above 1Gb/s. To the authors’ knowledge, this is the first implementation of a FEC decoder onto an FPGA target at information throughputs superior to 1Gb/s. Previously, a turbo decoder included in a 12.4Gb/s optical setup was presented. Since only a part of the transmitted data are actually coded, the information throughput of the decoder is only 156Mb/s.