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Communication Dans Un Congrès Année : 2015

Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology

Résumé

This paper aims to provide reliability projections and modeling for wearout current consumption and oxide lifetime (or programming time) under programming conditions regarding OTP memories perimeter. TDDB reliability methodology have been carried out to high voltages and the power law dependent T BD equations terms have been discussed. Adjustments focusing on the temperature impact on voltage acceleration offer us a compact model for TDDB HV.
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Dates et versions

hal-02153569 , version 1 (12-06-2019)

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Antoine Benoist, S. Denorme, X. Federspiel, Bruno Allard, P. Candelier. Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology. IRPS, Apr 2015, Monterey CA, United States. pp.GD.3.1-GD.3.5, ⟨10.1109/IRPS.2015.7112804⟩. ⟨hal-02153569⟩
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