Efficient Arbitrary Sample Rate Conversion for Multi-Standard Digital Front-Ends - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2019

Efficient Arbitrary Sample Rate Conversion for Multi-Standard Digital Front-Ends

Résumé

In this paper, we study the hardware implementation of arbitrary sample rate conversion (ASRC) using recently proposed variable fractional delay filter (V-FDF) structures. The most commonly used solution to implement V-FDFs has been the Farrow structure for the last three decades. In this work, we develop and compare the implementations of different recently proposed V-FDF options based on the Newton structure. These implementations are done on both ASIC and FPGA targets. The obtained results show that the recently proposed solutions offer better ASRC performance while using up to 3 times less resources relatively to the classical Farrow structure. The generic nature of these filters make them suited for a large number of standards.
Fichier principal
Vignette du fichier
NEWHRW.pdf (481.57 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-02124512 , version 1 (09-05-2019)

Identifiants

Citer

Ali Zeineddine, Stéphane Paquelet, Amor Nafkha, Pierre-Yves Jezequel, Christophe Moy. Efficient Arbitrary Sample Rate Conversion for Multi-Standard Digital Front-Ends. IEEE NEWCAS Conference 2019, Jun 2019, Munich, Germany. ⟨10.1109/NEWCAS44328.2019.8961230⟩. ⟨hal-02124512⟩
134 Consultations
474 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More