Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons - Archive ouverte HAL
Journal Articles EURASIP Journal on Advances in Signal Processing Year : 2013

Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons

Hanen Chenini
  • Function : Author
  • PersonId : 970443
Lab-STICC_UBO_CACS_MOCS
Institut Pascal
Jean Pierre Dérutin
  • Function : Author
Institut Pascal
Romuald Aufrère
Institut Pascal
Roland Chapuis
Institut Pascal

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Automatic Signal and Image processing
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https://hal.science/hal-02115059

Submitted on : Tuesday, February 27, 2024-6:20:05 PM

Last modification on : Tuesday, August 27, 2024-12:56:24 PM

Long-term archiving on : Tuesday, May 28, 2024-7:25:45 PM

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hal-02115059 , version 1 (27-02-2024)

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Hanen Chenini, Jean Pierre Dérutin, Romuald Aufrère, Roland Chapuis. Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons. EURASIP Journal on Advances in Signal Processing, 2013, 2013 (1), ⟨10.1186/1687-6180-2013-153⟩. ⟨hal-02115059⟩

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