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Communication Dans Un Congrès Année : 2018

Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

Résumé

This work explores, for the first time, wafer level variability of the gate leakage current in advanced FD-SOI MOSFETs. A simple model based on WKB approximation is introduced to model the leakage current and its variance. IL/HK variability segregation is presented using split C-V and gate current data without any dedicated test structures.
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Dates et versions

hal-02065295 , version 1 (12-03-2019)

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Krishna Pradeep, T. Karatsori, T. Poiroux, A. Juge, P. Scheer, et al.. Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs. 2018 ESSDERC - 48th European Solid-State Device Research Conference (ESSDERC), Sep 2018, Dresden, Germany. pp.242-245, ⟨10.1109/ESSDERC.2018.8486847⟩. ⟨hal-02065295⟩
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