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Communication Dans Un Congrès Année : 2014

Mismatch trends in 20nm gate-last bulk CMOS technology

Résumé

In this work Vt and β mismatch for the 20 nm Gate-last bulk CMOS technology are investigated for the first time. Our results indicate that the 20 nm Gate-last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-first counterpart. Furthermore, the evolution of the Vt and β mismatch parameters, iA ΔVt and iA Δβ/β , is analyzed as a function of EOT (Tox) from the 90 nm technology node down to the 20 nm technology node. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot iA ΔVt vs EOT is observed from the 28 nm Gate-first technology, with such offset approaching zero for the 20 nm Gate-last technology node. This indicates evidence of a huge decrease in the mismatch contribution of the gate material.
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Dates et versions

hal-02048981 , version 1 (26-02-2019)

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Lama Rahhal, Aurélie Bajolet, Jean-Philippe Manceau, Julien Rosa, Stéphane Ricq, et al.. Mismatch trends in 20nm gate-last bulk CMOS technology. 2014 15th International Conference on Ultimate Integration on Silicon (ULIS), Apr 2014, Stockholm, Sweden. pp.133-136, ⟨10.1109/ULIS.2014.6813916⟩. ⟨hal-02048981⟩
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