Innovative tunnel FET architectures - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2018

Innovative tunnel FET architectures

Résumé

We propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD. The extension of the source (anode) at the bottom of the body generates vertical band-to-band tunneling with a very steep slope and higher ION than lateral tunneling, but only for gate lengths longer than 100 nm. Using a heavily doped boron thin layer at the bottom increases ION even for aggressive gate lengths. Implementation of a tip in the source provides performance similar to the reference TFET. TCAD simulation using SiGe instead of Si shows current drive increase when using the thin boron layer for very thin channels, even for shorter gate lengths.
Fichier non déposé

Dates et versions

hal-02007301 , version 1 (05-02-2019)

Identifiants

Citer

Carlos Diaz Llorente, Sébastien Martinie, Sorin Cristoloveanu, Jean-Pierre Colinge, Cyrille Le Royer, et al.. Innovative tunnel FET architectures. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Mar 2018, Granada, Spain. pp.25-28, ⟨10.1109/ULIS.2018.8354725⟩. ⟨hal-02007301⟩
21 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More