Article Dans Une Revue Solid-State Electronics Année : 2016

Back-gate effects and mobility characterization in junctionless transistor

Résumé

This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation.

Dates et versions

hal-02003150 , version 1 (01-02-2019)

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Mukta Singh Parihar, Fanyu Liu, Carlos Navarro, Sylvain Barraud, Bawedin M., et al.. Back-gate effects and mobility characterization in junctionless transistor. Solid-State Electronics, 2016, 125, pp.154-160. ⟨10.1016/j.sse.2016.07.016⟩. ⟨hal-02003150⟩
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