Noise-induced dynamic variability in nano-scale CMOS SRAM cells
Résumé
The lack of dynamic stability in memory circuits such as the Static Random Access Memory can lead to read/write failures or power supply limitations. In this work, the impact of low-frequency and random telegraph noise on the dynamic variability of a single SRAM cell is examined for the first time. The dependence on device noise level, speed and duration of operation is investigated, using the Supply Read Retention Voltage and the Read Static Noise Margin as stability metrics. New measurement and simulation methods are also presented. The results are compared to the mismatch-induced variability, revealing the importance of noise-related dynamic instabilities in advanced circuits.