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Communication Dans Un Congrès Année : 2015

Non-volatility for ultra-low power asynchronous circuits in hybrid CMOS/magnetic technology

Résumé

This paper addresses the power reduction techniques for the ultra-low power integrated circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi-zero leakage consumption, almost instant back-up and wake-up time and will be robust to unstable supply environments. This paper presents the implementation of the non-volatile C-element and Half-Buffer, based on hybrid technology incorporating 28nm CMOS FD-SOI and 40nm STT-MRAM magnetic technologies. We discuss our recent simulation results of the proposed non-volatile blocks and as well more complex structures based on them. We derive the criteria of the implementation efficiency and compare the conventional asynchronous blocks with the proposed non-volatile ones.
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hal-01976670 , version 1 (10-01-2019)

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E. Zianbetov, E. Beigne, G. Di Pendina. Non-volatility for ultra-low power asynchronous circuits in hybrid CMOS/magnetic technology. 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, May 2015, Mountain View, United States. pp.139-146, ⟨10.1109/ASYNC.2015.27⟩. ⟨hal-01976670⟩
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