Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard - Archive ouverte HAL
Communication Dans Un Congrès Année : 2018

Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard

Résumé

An integrated CMOS Wide Band Arbitrary Waveform Generator (AWG) for Carrier Aggregation purpose is proposed and demonstrated. This work is designed to target the sub-6 GHz 5G standard and is implemented in 65nm CMOS technology from TSMC. A piecewise linear approximation of the modulated signal, using Noise Shaping Riemann (NSR) algorithm, is processed. Its principle is based on the integration of constant current steps into a capacitive load. Moreover, the ability to generate multi-carrier signal is also demonstrated with measurements of a minimum 28dB SNDR on multi-carrier signal confirming the theory. EVM measurements depict a maximum of 16% for a data rate of 50MS=s for carrier frequencies up to 3:2Ghz. The Riemann Pump consumes less than 1mW for a reduced die area.
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Dates et versions

hal-01964931 , version 1 (24-12-2018)

Identifiants

  • HAL Id : hal-01964931 , version 1

Citer

Pierre Bisiaux, Francois Rivet, Yoan Veyrac, Yann Deval. Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard. IEEE International Conference on Electronics Circuits and Systems, Dec 2018, Bordeaux, France. ⟨hal-01964931⟩
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