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Article Dans Une Revue Solid-State Electronics Année : 2012

Revisited approach for the characterization of Gate Induced Drain Leakage

Résumé

This work presents a re-investigation of the electrical characterisation of Gate Induced Drain Leakage (GIDL) [1][2]. The limits of the previously proposed extraction methods are underlined and a new approach is introduced. This new approach enables a better extraction of the GIDL parameters compared to the conventional methods, provided that a new step of electric field extraction is used. Finally, the experimental application of this new approach confirms its ability to quantify the impact of trap assisted tunnelling on GIDL.
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Dates et versions

hal-01959351 , version 1 (18-12-2018)

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Quentin Rafhay, Cuiqin Xu, Perrine Batude, Mireille Mouis, Maud Vinet, et al.. Revisited approach for the characterization of Gate Induced Drain Leakage. Solid-State Electronics, 2012, 71, pp.37-41. ⟨10.1109/ULIS.2011.5757994⟩. ⟨hal-01959351⟩
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