Article Dans Une Revue Solid-State Electronics Année : 2018

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

Résumé

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

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Dates et versions

hal-01948041 , version 1 (07-12-2018)

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Krishna Pradeep, Thierry Poiroux, Patrick Scheer, Andre Juge, Gilles Gouget, et al.. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements. Solid-State Electronics, 2018, 145, pp.19-28. ⟨10.1016/j.sse.2018.04.001⟩. ⟨hal-01948041⟩
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