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Article Dans Une Revue Solid-State Electronics Année : 2015

A comparative mismatch study of the 20nm Gate-Last and 28nm Gate-First bulk CMOS technologies

Résumé

In this work the threshold voltage (Vt), the current gain factor (β), and the drain current (ID) mismatch trends for 20 nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the β mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and β, and on the contributions of the transconductance divided by the drain current (Gm/ID) and the source drain series resistance (Rsd) terms. The 20 nm Gate-Last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the Vt and β mismatch parameters, iAΔVt and iAΔβ/β, is further analyzed as a function of the electrical oxide thickness EOT (Tox) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot of iAΔVt as a function of EOT is observed starting at the 28 nm Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances.
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Dates et versions

hal-01947642 , version 1 (07-12-2018)

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Lama Rahhal, Aurélie Bajolet, Jean-Philippe Manceau, Julien Rosa, Stéphane Ricq, et al.. A comparative mismatch study of the 20nm Gate-Last and 28nm Gate-First bulk CMOS technologies. Solid-State Electronics, 2015, 108, pp.53-60. ⟨10.1016/j.sse.2014.12.006⟩. ⟨hal-01947642⟩
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