Sub-threshold operation of circuits becomes more and more attractive due to the ultra-low power consumption. Static Random Access Memory (SRAM) faces an important limitation in read access time that prevents high frequency operation and the possible applications. The read access time under ultra-low voltage (ULV) operation is mainly dictated by the read current of the SRAM bit cell and the bit line effective capacitance. The full swing sensing is a practical approach to circumvent the poor performances of sense amplifiers (SA) under ULV operation. This paper details first the optimization of a differential voltage-sense amplifier under ULV for SRAMs with differential bit lines. Second an unbalanced voltage-sense amplifier is presented for single-ended reading under ULV. Both circuits exploit the benefit of 28nm FDSOI and back biasing technique to improve SAs' performances, namely the delay. Both ultra-wide voltage-range SAs achieve satisfying operation down to 280mV power supply. Simulation results are presented regarding a 1K×32 L1 cache test chip to be fabricated in 28FDSOI technology.