A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS
Abstract
Clique-based neural networks implement low- complexity functions working with a reduced connectivity be- tween neurons. Thus, they address very specific applications operating with a very low energy budget. This paper proposes a flexible and iterative neural architecture able to implement multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in a ST 65-nm CMOS ASIC and validated in the context of ECG classification. The network core reacts in 83ns to a stimulation and occupies a 0.21mm 2 silicon area.