I. INTRODUCTION In the last years, the integration of specialized hardware accelerators in Multiprocessor System-on-Chip (MpSoC) led to a new kind of architectures combining both software (SW) and hardware (HW) computational resources. For these new Heterogeneous MpSoC (HMpSoC) architectures, performance and energy consumption depend on a large set of parameters such as the HW/SW partitioning, the type of HW implementation or the communication cost. Design Space Exploration (DSE) consists in adjusting these parameters while monitoring a set of metrics (execution time, power, energy efficiency) to find the best mapping of the application on the targeted architecture. With the shift from performance-aware to energy-aware designs, DSE frameworks started to integrate state-of-the-art power models. These power modeling tools require simulations of the application, which drastically increases the exploration time. This work introduces a DSE method based on an analytical power model to circumvent the computation time bottleneck of state-of-the-art power models.