High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2018

High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques

Résumé

Field Programmable Gate Arrays (FPGAs) offer very efficient fault-tolerance strategies based on partial reconfiguration. These strategies use dedicated spare resources at different levels to replace faulty elements. A method to determine if the targeted level of reliability can be obtained is then required. In this paper, we generalize the reliability estimation formulas for the state-of-the-art fault tolerance techniques based on partial reconfiguration. We use those formulas to estimate the bounds of the different techniques in terms of reliability level and bitstream overhead. This work makes possible to evaluate early in the design-flow the achievable mission time for a given number of faults per time unit. Thanks to its generality, our approach can be derived for future new partial reconfiguration approaches.

Domaines

Electronique
Fichier non déposé

Dates et versions

hal-01797245 , version 1 (22-05-2018)

Identifiants

Citer

Tien Thanh Nguyen, Mathieu Thevenin, Anthony Mouraud, Gwenolé Corre, Olivier Pasquier, et al.. High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques. Reconfigurable Architectures Workshop (RAW 2018), May 2018, Vancouver, Canada. pp.202-205, ⟨10.1109/IPDPSW.2018.00038⟩. ⟨hal-01797245⟩
130 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More