The aim of this work is to investigate non-stationary transport effects occurring in 50 nm MOSFET technology and to provide guidelines for technology optimization in order to maximize the impact of these effects on device performances. We analyze quantitatively the real impact of technology on the needed level of accuracy for carrier transport modeling and we show which recipes must be used to evaluate the performances of advanced device architectures. The original point of this work is the investigation of technology influence on injection velocity at source side and on drain current. The results open the perspective of specific engineering of access regions in order to take full advantage of nonstationary effects on the drain current.