In this work, the degradation of electrical performances of Double-Gate MOSFET due to the fringing induced barrier lowering (FIBL) effect induced by high-kappa gate dielectrics is investigated using a two-dimensional quantum-mechanical simulation code. Our numerical results show that all electrical parameters, such as the threshold voltage (V-T), device immunity to short-channel effects, off-state current (I-off), and subthreshold slope (S) are degraded when kappa increases (3.9 < kappa < 100). This degradation is both function of the channel length and the gate dielectric stack composition (number of layers, kappa value). In particular, it is shown that the introduction of a thin (< 1 nm thick) interfacial oxide layer can reduce or even completely suppress the FIBL for a given equivalent oxide thickness of the gate dielectric stack. (c) 2005 Elsevier B.V. All rights reserved.