We propose generic architectures for memory-efficient Uniformly reweighted a posteriori probability (URAPP) Decoders of Low Density Parity Check (LDPC) codes, with the bit error rate close to Belief propagation decoding. The architectures enables a trade off between the throughput, computational and hardware resources. As a special case, we derive previously proposed flooding schedule URAPP decoder and propose new type of the URAPP decoder which uses shuffled scheduling. We conduct a rigorous complexity analysis and provide new formulas for the URAPP decoder throughput in terms of hardware resources and memory requirements. The analysis confirms that the shuffled decoder represents an optimal solution if the hardware resources are limited, which makes it attractive in practical applications. The results are verified by simulations for the case of finite geometry LDPC codes.