FinFET technology has become the most promising semiconductor technology alternative to CMOS planar at highly scaled nodes (e.g. below 20nm). FinFET technology offers higher performance with lower leakage thanks to a better channel control obtained by wrapping a metal gate around a thin fin. In this paper, bridge defects in FinFET based logic cells are investigated. The impact of the use of Middle-Of-Line (MOL) interconnections and multi-fin and multi-finger devices pose a challenge on the detection of bridge defects. They influence the likelihood of occurrence of these defects, and make them more difficult to detect than in CMOS planar technology. Even more some defects unlikely to appear in planar CMOS now become more likely to occur. A metric called Bridge Defect Criticality (BDC) is used to identify the most critical bridge defects. Actions may be taken over these defects to increase their fault tolerance or testability.