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Article Dans Une Revue IEEE Journal of Solid-State Circuits Année : 2017

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

Ben Keller
  • Fonction : Auteur
Brian Zimmer
  • Fonction : Auteur
Jaehwa Kwak
  • Fonction : Auteur
Alberto Puggelli
  • Fonction : Auteur
Yunsup Lee
  • Fonction : Auteur
Milovan Blagojevic
  • Fonction : Auteur
Stevo Bailey
  • Fonction : Auteur
Pi-Feng Chiu
  • Fonction : Auteur
Palmer Dabbelt
  • Fonction : Auteur
Colin Schmidt
  • Fonction : Auteur
Elad Alon
  • Fonction : Auteur
Krste Asanovic
  • Fonction : Auteur
Borivoje Nikolic
  • Fonction : Auteur

Résumé

This paper presents a RISC-V system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power management implemented in a 28 nm fully depleted silicon-on-insulator process. A fully integrated simultaneous-switching switched-capacitor DC-DC converter supplies an application core using a clock from a free-running adaptive clock generator, achieving high system conversion efficiency (82%-89%) and energy efficiency (41.8 double-precision GFLOPS/W) while delivering up to 231 mW of power. A second core serves as an integrated power-management unit that can measure system state and actuate changes to core voltage and frequency, allowing the implementation of a wide variety of power-management algorithms that can respond at submicrosecond timescales while adding just 2.0% area overhead. A voltage dithering program allows operation across a wide continuous voltage range (0.45 V-1 V), while an adaptive voltage-scaling algorithm reduces the energy consumption of a synthetic benchmark by 39.8% with negligible performance penalty, demonstrating practical microsecond-scale power management for mobile SoCs.

Dates et versions

hal-01694209 , version 1 (26-01-2018)

Identifiants

Citer

Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, et al.. A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. IEEE Journal of Solid-State Circuits, 2017, 52 (7), pp.1863-1875. ⟨10.1109/JSSC.2017.2690859⟩. ⟨hal-01694209⟩
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