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Article Dans Une Revue Microelectronic Engineering Année : 2017

Towards fabrication of 3D isotopically modulated vertical silicon nanowires in selective areas by nanosphere lithography

Gerry Hamdana
  • Fonction : Auteur
Tobias Suedkamp
  • Fonction : Auteur
Marion Descoins
  • Fonction : Auteur
Lorenzo Caccamo
  • Fonction : Auteur
Mails Bertke
  • Fonction : Auteur
Hutomo Suryo Wasisto
  • Fonction : Auteur
Hartmut Bracht
  • Fonction : Auteur
Erwin Peiner
  • Fonction : Auteur

Résumé

An improved nanofabrication processing technique for realization of vertically aligned silicon nanowires (SiNW5) by colloidal lithography is reported in this work. Microstructure pattern arrays are prepared on the substrate allowing selective deposition of polystyrene (PS) nanoparticles. Using PSS/PDDA/PSS-layer, surface properties can be modified resulting in an enhanced hydrophilicity of the silicon substrate, which is followed by high surface coverage up to-83% after particle transfer. During the fabrication, we demonstrate full control of the mask dimension providing excellent control of nanostructure feature size by inductively coupled plasma (ICP) reactive ion etching (RIE) process at cryogenic temperature. Finally, this combined approach of bottom-up and top-down methods offers simple and direct nanoscale processing steps with low-cost and great reproducibility, enabling high density fabrication of nanostructure (similar to 10(9) SiNW/cm(2)) within certain area. This preparation route of the SiNWs was applied to isotopically controlled silicon layers grown epitaxially on Si substrates. Atom probe tomography of these SiNWs reveal that the isotope layer ordering is preserved by the NW fabrication route. (C) 2017 Elsevier B.V. All rights reserved.
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Dates et versions

hal-01694208 , version 1 (26-01-2018)

Identifiants

Citer

Gerry Hamdana, Tobias Suedkamp, Marion Descoins, Dominique Mangelinck, Lorenzo Caccamo, et al.. Towards fabrication of 3D isotopically modulated vertical silicon nanowires in selective areas by nanosphere lithography. Microelectronic Engineering, 2017, 179, pp.74-82. ⟨10.1016/j.mee.2017.04.030⟩. ⟨hal-01694208⟩
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