Large memories require too much resources to be fully extracted and simulated. In this paper we present an accurate power and timing modeling technique that reduces significantly characterization resources. The model is based on current controlled generators, and can be used in several regular structures. Low-power memories are easier to characterize using this technique, since they are block partitioned. Moreover, this modeling technique is fully parameterable and is very useful to efficiently develop and optimize memory compilers. It has been successfully applied to characterize and improve performances of a low-power ROM compiler.