Higher switching speed of power devices in series connection achieved by modifying the gate driver architecture
Résumé
This paper presents the study on gate driver circuitries implemented to drive power devices in series
connection with the objective to minimize the conducted EMI perturbations and as well to improve the
switching speed of the power devices. More specifically, the propagation paths of parasitic currents
generated under very high switching speed are studied in different configurations trying to reduce the
parasitic capacitance of each gate driver circuit with respect to ground/control reference potential and
to minimize the common mode currents. In complex power converters, multi-cell, multi-level or even
series connection of power devices, many driver circuits are required and implemented. Similarly, in
such converters, there are several dv/dt sources generated at different floating points that are exiting
the isolated barriers of the gate drivers (supplies and control signal isolation units) which mean that
conducted EMI perturbations can be amplified and the switching speed of the power devices could be
affected by multi-parasitic capacitances. Based on previous works, the paper analyses the best possible
configurations to minimize the common mode currents in series connected transistor topologies and to
reduce the parasitic capacitance of the gate driver circuitries leading as well to a significant improvement
of the switching speed of the power devices. In this article, experimental validations are used to approve the analysis.