This paper describes a new technique to reduce the number of simulations required during analog fault simulation. The method takes into account process parameter variations and aims to reduce the number of the computational expensive Monte Carlo simulations often required during analog fault simulation. In section I a review of the state of the art is presented, section II and III introduce the algorithm and describe the methodology of our approach. The results on CMOS 2-stage opamp and conclusions are given in sections IV and V.