In this paper, the design procedure for a third-order continuous-time /spl Sigma//spl Delta/ modulator with RZ feedback is described. The circuit is realized using continuous-time current-mode integrators and DACs with switched-current sources. A design method to find the minimum biasing current required to achieve the desired dynamic range is presented. With a sampling frequency of 25.6 MHz, the circuit is expected to achieve 84 dB of dynamic range for a 100 kHz bandwidth input signal. The circuit operates from a power supply of 1.7 V and consumes 7.4 mW in a 0.35 /spl mu/m CMOS process.