Use of MutiPhase Stability Intervals to handle Crosstalk with the Timing Analyzer hiTas
Résumé
This paper presents techniques to include the impact of crosstalk on timing verification of VLSI. We propose delay models for the victim driver gate, loaded through a resistive wire, when noise is injected from aggressor nets. A special care has been taken in order to minimize CPU time and data storage size. The proposed method was implemented with the hierarchical timing analyzer HiTAS and the stability analyzer STB by Avertec, a spin-off company of UPMC. Results on three real circuits are presented to illustrate the method.