Many-core processors are expected to be hardware targets to support the execution of real-time applications. In a many-core processor, cores communicate through a Network-On-Chip (NoC), which offers high bandwidth and scalability, but also introduces contentions leading to additional variability to task execution times. Such contentions also strongly increase the pessimistic trend of worst case execution time estimation. Consequently, modeling and analysis of network contentions interferences on many-core processors is a challenge to support real- time applications. In this article, we formalize a dual task and flow model called DTFM. From the specification of a real-time application composed of a set of tasks and their communication dependencies, DTFM allows us to compute flow requirements and to assess predictability of the tasks. DTFM is extensible enough to be adapted to various NoCs and task models, allowing designers to compare candidate software and NoC architectures. Furthermore, we introduce an original validation approach based on the cross-use of a task level real-time scheduling analysis tool and a cycle-accurate SystemC NoC simulator.