The topical problem of effective verification of digital circuits of different physical systems remains a hot topic. Devices ranging from embedded components to perform specific tasks or experiments to modern communication clusters used for data transmission are concerned. The method of synthesis of the test sequences is based on injection of faults into a reference circuit and deriving a corresponding distinguishing sequence which detects this fault. The method is known as mutation testing and is widely used for the synthesis of high-quality verification tests for digital circuits. Naturally, test suits that detect faults of various classes, and larger amount of faults, are of greater interest. The paper studies the correlation between different test suits derived for different mutant types. The considered fault types include 1) single stuck-at faults, 2) bridges, and 3) hardly detectable faults, i.e., slightly modifying the behavior of a single circuit gate. Tests for detecting faults of each type are derived for the B01-B10 benchmark package (ITC'99 benchmarks (Second Release)), which are components of physical systems intended for various applications including processing of data obtained, load balancing systems, etc. Experiments aim to access the fault coverage of the test derived for one mutant type against faults of other types. It is shown experimentally that the synthesis of tests of one type, including a single stuck-at fault test, is insufficient, because its fault coverage for faults of other types cannot exceed 60%