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Communication Dans Un Congrès Année : 2016

Testing logic circuits at different abstraction levels : an experimental evaluation

Résumé

The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones
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Dates et versions

hal-01450771 , version 1 (31-01-2017)

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Sergey Smolov, Jorge Eleazar Lopez Coronado, Natalia Kushik, Nina Yevtushenko, Alexander Kamkin, et al.. Testing logic circuits at different abstraction levels : an experimental evaluation. EWDTS 2016 : IEEE East-West Design & Test Symposium, Oct 2016, Yerevan, Armenia. pp.1 - 4, ⟨10.1109/EWDTS.2016.7807687⟩. ⟨hal-01450771⟩
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