Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm - Archive ouverte HAL
Article Dans Une Revue IEEE Transactions on Computers Année : 2018

Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm

Vincent Migliore
Maria Mendez Real
Vianney Lapotre
Arnaud Tisserand
Guy Gogniat

Résumé

Somewhat Homomorphic Encryption (SHE) schemes can be used to carry out operations on ciphered data. In a cloud computing scenario, personal information can be processed secretly, inferring a high level of confidentiality. The principle limitation of SHE is the size of ciphertext compared to the size of the message. This issue can be addressed by using a batching technique that “packs” several messages into one ciphertext. However, this method leads to important drawbacks in standard implementations. This paper presents a fast hardware/software co-design implementation of an encryption procedure using the Karatsuba algorithm. Our hardware accelerator is 1.5 times faster than the state of the art for 1 encryption and 4 times faster for 4 encryptions.

Dates et versions

hal-01427639 , version 1 (05-01-2017)

Identifiants

Citer

Vincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, et al.. Hardware/Software co-Design of an Accelerator for FV Homomorphic Encryption Scheme using Karatsuba Algorithm. IEEE Transactions on Computers, 2018, 67 (3), pp.335-347. ⟨10.1109/TC.2016.2645204⟩. ⟨hal-01427639⟩
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