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Communication Dans Un Congrès Année : 2014

Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example

Résumé

Asynchronous circuits exhibit considerable advantages over their synchronous counterparts, like lower dynamic power and inherent variation tolerance, which makes them increasingly interesting. Their fault-tolerance behavior, however, is not yet fully explored. In particular, temporal masking, as seen with synchronous circuits, seems to be completely non-existent in asynchronous logic. Instead, there seem to be other masking mechanisms in the control structure that establish an extra barrier for transient fault propagation. In this paper we will explore these masking mechanisms in a qualitative as well as quantitative manner. To this end we first analyze the behavior of a Muller C-element, one fundamental building block in asynchronous designs. In a next step we evaluate the behavior of a chain of these elements, forming a so-called Muller pipeline, the basic control structure of many asynchronous designs, under transient faults. To validate our theoretical findings we inject radiation induced single event transients (SETs) in an extensive simulation campaign. The results show that the SET susceptibility of the Muller pipeline is indeed state dependent. This knowledge can be leveraged to improve, e.g., the radiation hardness of asynchronous circuits by preferring the more robust states in their design wherever possible.
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Dates et versions

hal-01400621 , version 1 (22-11-2016)

Licence

Paternité - Pas d'utilisation commerciale

Identifiants

  • HAL Id : hal-01400621 , version 1

Citer

A. Steininger, V.S. Veeravalli, D. Alexandrescu, E. Costenaro, Lorena Anghel. Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. 32nd IEEE International Conference on Computer Design (ICCD'14), Oct 2014, Seoul, North Korea. pp.61-67. ⟨hal-01400621⟩

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