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Communication Dans Un Congrès Année : 2015

Application-independent testing of multilevel interconnect in mesh-based FPGAs

Résumé

This paper presents a BIST scheme for a new hierarchical interconnect topology in mesh FPGAs. The proposed technique ensures full test and diagnosis by performing selection of test paths. It uses 2×2 adjacent logic resources. Using this scheme, any N×N FPGA array can be further tested by N parallel 2×2 array procedure which ultimately reduces the test time. The efficiency of this scheme is evaluated in terms of the number of configurations required for a complete testing of global interconnect in cluster-based FPGAs for different cluster sizes. Automated tools are developed to generate the test configuration bitstreams and to integrate them into a standard FPGA CAD flow. Simulation results show that 100% test coverage for stuck-at and pair-wise bridging faults can be achieved with high diagnostic resolution.
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Dates et versions

hal-01400596 , version 1 (22-11-2016)

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Paternité - Pas d'utilisation commerciale

Identifiants

  • HAL Id : hal-01400596 , version 1

Citer

Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel. Application-independent testing of multilevel interconnect in mesh-based FPGAs. IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6. ⟨hal-01400596⟩

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