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Communication Dans Un Congrès Année : 2000

Generic architecture platform for multiprocessor embedded system-on-chip design

Résumé

In this paper, we present a generic architecture model for multiprocessor embedded system-on-chip design. The use of this model as a template in a system design environment allows for efficient generation of multiprocessor architectures. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of application. In addition, it allows for reusability of pre-designed blocks and automatic architecture generation. This paper focuses on the definition of the architecture model. The feasibility and effectiveness of this architecture model are illustrated by a significant demonstration example.
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Dates et versions

hal-01381242 , version 1 (14-10-2016)

Licence

Paternité - Pas d'utilisation commerciale

Identifiants

  • HAL Id : hal-01381242 , version 1

Citer

Amer Baghdadi, Nacer-Eddine Zergainoh, D. Lyonnard, Ahmed Jerraya. Generic architecture platform for multiprocessor embedded system-on-chip design. International Workshop on Distributed and Parallel Embedded Systems (DIPES'00), Oct 2000, Paderborn, Allemagne. pp.53-64. ⟨hal-01381242⟩

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