With the global trend towards digital systems, designer's goal is to manage the system on chip complexity in accordance with the time to market constraint. Multi-FPGA hardware prototyping is an important feature to validate the design before reaching the fabrication phase. However, since the design is partitioned into multi-FPGA platform, the system frequency of the prototyped design is dramatically decreased due to the inter-FPGA communications. In fact, the way in which the design is partitioned affects the number of inter-FPGA signals and the critical path delay. In this paper, we propose a prototyping environment for multi-FPGA platforms. The partitioner tool is constrained so that it tries to find the best trade off between criteria that affects the system frequency. The resulting inter-FPGA signals are routed using an iterative routing algorithm. If the number of these signals exceeds the number of available traces between FPGAs, multiplexing IPs are inserted in the sending and receiving FPGA in order to transmit several signals through the same physical wire.