Multi-FPGA boards suffer from the limited bandwidth between FPGAs due to the limited number of I/Os. Indeed, when partitioning a design into multi-FPGA platform, the number of inter-FPGA signals is bigger than the number of available tracks on the board. These signals should be routed using a time-division-multiplexing technique in order to spare the FPGA I/Os which lowers the system frequency. The way in which the signals are routed and sent between each pair of FPGA affects the performance of the prototyping system. In this paper, we propose a routing methodology to route all the cut nets based on the selection of signals which are qualified/unqualified for multiplexing. After defining a routing path for each inter-FPGA signals, dedicated IOSERDES are inserted into the sending and receiving FPGA to speed up the transmission of the signals. This new approach improves the system frequency by an average of 11 % compared to a common approach based on obstacle avoidance. In addition, the fact of using IOSERDES based IP improves the system frequency by an average of 250 % compared to multiplexer based IP.