This work address the fault tolerance topic in the GPS context. Starting from a noiseless GPS receiver, redundant mechanisms can be added to design a more resilient GPS receiver in the presence of errors due to process, voltage and temperature (PVT) variations. These mechanisms are based on different layer of abstraction to guarantee a mutual trade-off of system performance (quality of the position given by the GPS receiver), hardware reliability and implementation complexity. An Application-specific integrated circuit (ASIC) will be designed with two versions of the GPS receiver: the standard version, and a complex version where fault tolerant techniques are added to make the GPS receiver more tolerant to errors.