Hardware runtime verification of embedded software in SoPC
Résumé
This paper discusses an implementation of runtime
verification for embedded software running on a System-on-
Programmable-Chip (SoPC) composed of a microcontroller and
a FPGA. The goal is to verify at runtime that the execution of the
software on the microcontroller conforms to a set of properties.
To do so, a minimal instrumentation of the software is used
to send events to a set of monitors implemented in the FPGA.
These monitors are synthesized from a formal specification of the
expected behavior of the system expressed as a set of past-time
linear temporal logic (ptLTL) formula.
| Origine | Fichiers produits par l'(les) auteur(s) |
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