Hardware runtime verification of embedded software in SoPC - Archive ouverte HAL
Conference Papers Year : 2015

Hardware runtime verification of embedded software in SoPC

Abstract

This paper discusses an implementation of runtime verification for embedded software running on a System-on- Programmable-Chip (SoPC) composed of a microcontroller and a FPGA. The goal is to verify at runtime that the execution of the software on the microcontroller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesized from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formula.
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Dates and versions

hal-01307973 , version 1 (12-03-2020)

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Cite

Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement. Hardware runtime verification of embedded software in SoPC. 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), May 2016, Cracovie, Poland. SIES 2016 paper 16, ⟨10.1109/sies.2016.7509425⟩. ⟨hal-01307973⟩
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