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Communication Dans Un Congrès Année : 2009

Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC

Résumé

Motion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA.
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Dates et versions

hal-01306372 , version 1 (22-04-2016)

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Citer

Moez Kthiri, Hassen Loukil, Imen Werda, Ahmed Ben Atitallah, Samet Amine, et al.. Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC. SSD: International Multi-Conference on Systems, Signals & Devices, Mar 2009, jerba, Tunisia. ⟨10.1109/SSD.2009.4956714⟩. ⟨hal-01306372⟩
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