This paper presents a new environment for the exploration of domain-specific coarse-grained FPGAs. An architecture description mechanism is used to define a coarse-grained architecture. A software flow is used to map a netlist on the defined architecture. The software flow not only maps the instances of a target netlist on their respective blocks in the architecture, but also refines the position of the blocks on the architecture. This environment can also be used to define and optimize a domain-specific architecture for a set of netlists to be mapped on it at mutually exclusive times. A set of DSP test-benches are used to show the effectiveness of various techniques used in this work.