FPGA acceleration is a commonly used technology for high-performance scientific computing. It offers massive parallelism with low power requirements. One of the main issues with such an approach is interfacing accelerators implemented on FPGA fabric with a host application. This requires physical FPGA access and low-level communication interfaces. In this paper, we present Caasper, a scalable and flexible communication framework designed to provide shared access to FPGA resources over a TCP network, through high-level communication routines. Prototype implementation of the framework demonstrates its efficiency and its usability in high-throughput applications.