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Communication Dans Un Congrès Année : 2015

CAASPER: Providing Accessible FPGA-acceleration over the Network

Résumé

FPGA acceleration is a commonly used technology for high-performance scientific computing. It offers massive parallelism with low power requirements. One of the main issues with such an approach is interfacing accelerators implemented on FPGA fabric with a host application. This requires physical FPGA access and low-level communication interfaces. In this paper, we present Caasper, a scalable and flexible communication framework designed to provide shared access to FPGA resources over a TCP network, through high-level communication routines. Prototype implementation of the framework demonstrates its efficiency and its usability in high-throughput applications.
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Dates et versions

hal-01292792 , version 1 (23-03-2016)

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Valentin Mena Morales, Yahia Brakni, Pierre-Henri Horrein, Amer Baghdadi. CAASPER: Providing Accessible FPGA-acceleration over the Network. RSP 2015 : 26th IEEE International Symposium on Rapid System Prototyping, Oct 2015, Amsterdam, Netherlands. pp.68 - 75, ⟨10.1109/RSP.2015.7416549⟩. ⟨hal-01292792⟩
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